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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:23:07 09/21/2007 
-- Design Name: 
-- Module Name:    sl2host - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sl2host is Port ( 
	sysclk 		: in  STD_LOGIC;
        rst 		: in  STD_LOGIC;
	--
        addr 		: in  STD_LOGIC_VECTOR (31 downto 0);
        data_i 		: out  STD_LOGIC_VECTOR (31 downto 0);
        data_o 		: in  STD_LOGIC_VECTOR (31 downto 0);
	sel 		: in  STD_LOGIC; -- Select
        wr 		: in  STD_LOGIC; -- Write
        rd 		: in  STD_LOGIC; -- Read
	rdy 		: out  STD_LOGIC;
        -- Slot control and status
        slot_phi 	: out  STD_LOGIC;
        slot_cs 	: out  STD_LOGIC;
        slot_cs2 	: out  STD_LOGIC;
        slot_wr 	: out  STD_LOGIC;
        slot_rd 	: out  STD_LOGIC;
        slot_req 	: in  STD_LOGIC;
	-- Slot Data and Address
        slot_adl_t 	: out  STD_LOGIC;
        slot_adh_t 	: out  STD_LOGIC;
	slot_adl_i 	: in  STD_LOGIC_VECTOR (15 downto 0);
	slot_adh_i 	: in  STD_LOGIC_VECTOR (7 downto 0);
        slot_adl_o 	: out  STD_LOGIC_VECTOR (15 downto 0);
        slot_adh_o 	: out  STD_LOGIC_VECTOR (7 downto 0);
	--
        EXEMEMCNT 	: in  STD_LOGIC_VECTOR (15 downto 0)
	);
end sl2host;

architecture Behavioral of sl2host is

signal cs : std_logic;
signal cs2 : std_logic;

signal sel_cs : std_logic;
signal sel_cs2 : std_logic;

signal phi_cnt : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal phi_reload : STD_LOGIC_VECTOR (2 downto 0);
signal phi_int : STD_LOGIC := '0';

begin
	slot_phi <= phi_int;
	
	phi_reload <= 
		"111" when EXEMEMCNT(1 downto 0)="01" else
		"011" when EXEMEMCNT(1 downto 0)="10" else
		"001" when EXEMEMCNT(1 downto 0)="11" else
		"000";
		
	process (sysclk)
	begin
		if (rising_edge(sysclk)) then
			if (phi_cnt="000") then
				phi_cnt <= phi_reload;
				-- toggle or keep low
				phi_int <= not phi_int and (EXEMEMCNT(1) or EXEMEMCNT(0));
			else
				phi_cnt <= phi_cnt-"001";
			end if;	
		end if;
	end process;	
	
	--
	cs 		<= '1' when addr(27 downto 25) = "100" else '0'; -- 0xX8000000..0xX9FFFFFF
	cs2 		<= '1' when addr(27 downto 25) = "101" else '0'; -- 0xXA000000..0xXAFFFFFF
	slot_cs 	<= not (sel and cs);
	slot_cs2 	<= not (sel and cs2);
	slot_rd 	<= not rd;
	slot_wr 	<= not wr;
	-- output address or data
	slot_adl_o 	<= data_o(15 downto 0) when wr='1' else addr(15 downto 0);
	slot_adl_t	<= wr and cs;
	
	slot_adh_o 	<= addr(23 downto 16) when cs='1' else data_o(7 downto 0);
	slot_adh_t	<= wr and cs2;
	-- Read mux
	data_i(15 downto 0) <= slot_adl_i(15 downto 0) when cs='1' else (X"00" & slot_adh_i(7 downto 0));
	
	-- not impl!
	rdy <= '1';


end Behavioral;

